1. Field of Use
This invention relates to resolving access to a system bus which grants access on a priority basis. More particularly, the present invention pertains to gaining access to a system bus by a plurality of processing units which connect in common to a private bus.
2. Prior Art
Some systems have simplified bus communications on a single communications bus by utilizing a busy status line that is monitored by each device connected in the system. In one such system, when a device desired to send a message, it initially proceeds to busy out the busy status line, by causing a busy flag to be placed on the line. The device also checks the busy status line in order to ascertain whether a busy flag was already set. If the bus is busy, the device cannot transmit until the bus becomes free and the requesting device resets the bus busy flag for a retry interval. This arrangement is disclosed in U.S. Pat. No. 4,281,380.
While the above arrangement reduces contention, it is predicated on the use of a single communications bus. Further, the arrangement is primarily directed to preventing simultaneous transmission of messages resulting in interference.
When there have been more than one bus involved, the approach has generally been to contend for the different buses in a sequential manner. In some systems, the amount of contention time has been reduced. For example, U.S. Pat. No. 4,901,226, which is assigned to the same assignee, discloses an arrangement for enabling processing units which connect in common to a local bus to access a system bus through a bus interface unit. While the arrangement minimizes the time required for resolving local bus priority and system bus priority, it still requires the units which connect to the two buses to contend for bus access.
In such systems, it may be possible to provide separate bus interfaces. However, this requires a considerable amount of additional logic circuits. Also, it still requires the units to contend for access to at least one bus, such as the system bus.
A further option is to provide completely separate buses. This is an extremely costly solution, since it essentially doubles the amount of circuits and interface connections. Further, the memory units which are required to connect to both buses will still be required to sort out the requests received from both buses and establish the order in which the requests should be processed. This can lead to the issuance of waits to processing units when the memory is unable to process the processing unit request.
Accordingly, it is a primary object of the present invention to provide an improved method and apparatus for processing requests made by a processing unit which connects to more than one bus.
It is a further object of the present invention to provide an arrangement for processing requests from a plurality of processing units in a manner which eliminates contention between such units.